------ DRAFT------
User Guide
of
PCI/32-bit LVDS parallel interface
for
Flash ADC link system of BELLE SVD2
Yoshiji YASU
Online group, Institute of Particle and Nuclear Studies
High Energy Accelerator Research Organization (KEK)
July 2002

• Contents
• List of Tables
• List of Figures
• Introduction
  • Requirement to Flash ADC link system
    • Readout from Flash ADC system
    • Reduction of event data: Sparcification
    • Source node of BELLE event builder
  • Organization
• Hardware Specification
  • Functions
  • Components
    • Connector and Cable
    • LVDS driver/receiver : NS DS90LV031/32
    • Programmable Logic Device : ALTERA FLEX EPF10K30A
    • CMOS Asynchronous FIFO: IDT 7203
    • Others
  • Link protocol
    • Protocol Specification
    • Timing Specification
    • Link to FADC and the emulator
      • real FADC
      • FADC emulator
• Operation
  • I/O register map
  • I/O register detail
  • Operation procedure
• Linux Device Driver
  • Installation
    • How to get the distribution kit
    • How to compile and load the device driver
    • Identification of P-PCI-LV in PCI slot
    • Modification of driver parameters
  • User interface definition
    • open and close
      • open
      • close
    • ioctl
      • reset
      • put and get data
      • release control
      • dump contents of registers
      • reset FIFO
    • read and write
  • Examples
    • Explanation of read program
    • How to run the read and write programs
• References
• About this document ...