Hardware Specification

P-PCI-LV in Figure is a PCI interface for sending and receiving 32-bit data via a half duplex point-point LVDS link with 96-contact half-pitch connector and the cable[4,5,6].

 
Figure: P-PCI-LV  

The interface contains a ALTERA Programmable Logic Device (PLD)[7], which handles PCI bus and an external bus. It also includes FIFO[8] to store data temporarily between the PCI bus and the external bus. The protocol of the external bus is simple. It is a synchronous bus strobed by a clock signal.

• Functions
• Components
  • Connector and Cable
  • LVDS driver/receiver : NS DS90LV031/32
  • Programmable Logic Device : ALTERA FLEX EPF10K30A
  • CMOS Asynchronous FIFO: IDT 7203
  • Others
• Link protocol
  • Protocol Specification
  • Timing Specification
  • Link to FADC and the emulator
    • real FADC
    • FADC emulator