Protocol Specification

  Here is the protocol of data transfer between PC and FADC system. It assumes that the FADC system will send data to PC before the PC tries to read the data.

1. The FADC asserts XREQUEST first.
2. After PC (P-PCI-LV) asserts XREADY and XENABLE for receiving data from the FADC, the FADC asserts XVALID.
3. The FADC sends out the data with XCLOCK. The data are latched at the timing of the leading edges of the clock.
4. During the data transfer, PC deasserts XENABLE when the FIFO in P-PCI-LV becomes mostly-full. The mostly-full point reaches when size of data in FIFO becomes 7168 (8192 - 1024) bytes.
5. During the data transfer, the FADC can deassert XREQUEST when data in the FADC FIFO is empty. When XREQUEST is deasserted, PC will deassert XENABLE and XREADY for terminating the data transfer. At the time, PC can not read an unit of data ( N x event size, upto 128 kbytes ). Otherwise, PC will read data of the unit.
6. PC deasserts XREADY and XENABLE after reading the unit.
7. The FADC deasserts XVALID after the data transfer, which is followed by deassertion of XENABLE from PC.
8. The FADC will not deassert XREQUEST during data-taking except when the FIFO is empty.