Figure 
show the timing of XCLOCK,
XVALID, XENABLE and XDATA. The direction of data transfer
is from FADC to PC. XCLOCK, XVALID and XDATA are asserted
by FADC while XENABLE is asserted by PC.
Figure: Signal timing of the protocol
Here is an algorithm to avoid data loss when the FIFO in P-PCI-LV interface becomes FULL. The FIFO size is 8kB. Data from a FADC system may be sent to the interface over the 8kB. The interface will deassert XENABLE signal when the FIFO becomes "MOSTLY-FULL" during data transfer. The FADC system should provide to stop sending data. When the system is ready to stop it, the system should deassert XVALID. While the XVALID is asserted, PC will receive data from the FADC system and then store the data into FIFO even if the PC already deasserts XENABLE via P-PCI-LV interface. The FADC system will restart to send data to the interface at the leading edge of next XCLOCK after the system receives the asserted XENABLE.
The P-PCI-LV interface manages FIFO by providing some circuit to count the byte count of FIFO because the FIFO chip only provides three status of FIFO, namely FULL, half of FULL and EMPTY. The interface will count data in FIFO for managing data transfer at PCI bus. The clock used at the circuit is PCI clock (33 MHz). The period is 30 nsec. The circuit checks the leading edge and trailing edge of XCLOCK. If the frequency of XCLOCK is 12 MHz, the period is about 80 nsec and the edge should be detected in 30 nsec. The period of the edge is 40 nsec. The setup time of data is 30 nsec while the holding time is 14 nsec. When the frequency of XCLOCK is 20 MHz, the period is 50 nsec. The setup time should be 13 nsec while the holding time is 14 nsec.
The interface will send data of 64 bytes on PCI bus in burst mode at a time when FIFO has at least data of 64 bytes. It will also send data of 4 bytes when the FIFO only has data less than 64 bytes. In both cases, the interface will become PCI bus master.
Here is a way to send data from FADC to P-PCI continuously. XREQUEST, which is controlled by FADC, should be always asserted, namely, Low whenever next event data are available. FADC will assert XVALID when data to be sent is ready. On the other hand, P-PCI will assert XREADY and XENABLE when a read operation to P-PCI is executed. When P-PCI asserts XREADY and XENABLE, P-PCI will read data from FADC as XVALID is asserted. For an example, P-PCI will read 1000 bytes of data from FADC when the transfer count is set to 1000 bytes while the normal-end interrupt will occur. After P-PCI reads 1000 bytes of data, it will interrupt to CPU as normal-end interrupt.
Another issue is a handshake of XENABLE and XVALID.
Even if PC deasserts XENABLE for the completion of a data transfer,
FADC does not deassert XVALID immediately. Thus, P-PCI-LV will not
stop reading data from FADC immediately at the completion.
P-PCI-LV waits for the deassertion of XVALID and then stop reading.
During the assertion of XVALID, P-PCI-LV will read data from FADC
into the FIFO. Figure explains them.
Figure: Handshake of XENABLE and XVALID