Parallel CAMAC Project

Yoshiji Yasu
Online group, Institute of Particle and Nuclear Studies (IPNS), High Energy Accelerator Research Organization (KEK)
1-1 Oho, Tsukuba, Ibaraki 305-0801 Japan
Last Modified: August 11, 2003

| Introduction | Current status | Plan | Documents | Software | WEB sites |


What is Parallel CAMAC Project?

The aim of this project is to study a new parallel read-out system. One of the examples is a pipeline CAMAC controller. The architecture is based on Tx and Rx pipeline transfer. The crate controller can do CAMAC access in 1usec/cycle by using pipeline method. Over 20 years ago, intelligent CAMAC controllers called MBD-11 and CCS-11 had best access speed like ~1.2usec/CAMAC cycle. However, recent CAMAC interfaces such as TOYO CC-7x00 and Kintic 2917 have poor access speed because CAMAC interface did not adopt pipeline method while the pipeline method is already established in DAQ system. The idea is to implement Tx command input pipeline and Rx reply output pipeline between PCI and CAMAC. CAMAC command frames ( with data for write function ) are input from Tx command input pipeline via PCI, the commands are executed in 1 usec at CAMAC executor and then CAMAC reply frames with Q and X responses (, and data for read function ) are output to Rx reply output pipeline. As the result, a CAMAC operation will be done in 1 usec with small overhead as many frames.

The controller also has very simple DAQ function for event numbering, with Trigger signal input and Busyout signal output. The functionality enables a DAQ system with event numbering even if it includes the CAMAC system.

In first stage of the project, a pipeline CAMAC controller with PC104+ board computer is developed. The board computer is a PCM-9370 Tranmeta Crusoe based single board computer, which includes 500MHz Crusoe with 64 MB memory, 10/100 base-T Ethernet, USB, LCD, E-IDE, Flash Disk and so on.

PCI interface part includes a ALTERA FPGA. It consists of a Tx channel and a Rx channel. It also includes FIFO. On the other hand, CAMAC part includes a ALTERA FPGA. It consists of CAMAC executor, DAQ executor, LAM and DAQ Interrupt handlers. It also includes FIFO. The PCI interface is connected to the CAMAC part via a special protocol called CSP.

In next stage of the project, network link for parallel processing will be studied. The candidate is SpaceWire. The SpaceWire is a simple, point to point serial link with the switch fabric. Thus, it is scalable. PCI-SpaceWire interface will be developed.

Development Team

Current status

Pipeline CAMAC controller

VME/SpaceWire module developed by Osaka University

PCI/SpaceWire module




WEB sites