Frequently Asked Questions And Answers (Part 3): Products & Services
This is a monthly posting to comp.lang.vhdl containing information products and services for VHDL (commercial and public domain) Please send additional information directly to the editor:
edwin@ds.e-technik.uni-dortmund.de (Edwin Naroska)Corrections and suggestions are appreciated. Thanks for all corrections.
There are three other regular postings: part 1 lists general information on VHDL, part 2 lists books on VHDL, part 4 contains descriptions for a number of terms and phrases used to define VHDL.
This product list is never up to date it seems - please help to update it. This list is without any guarantee to be complete or correct. It is included to enable contacts to vendors. It does not contain version, quality or price information. (Please accept, that actually this information changes to fast -too much work to keep such information up to date, but if there is a volunteer willing to take this part...:-). If some kind of judgment is included ('specialist' for example) it's not my personal opinion but a remark from the vendor himself.
Contact: Peter Reintjes, Email: pbr@quintus.com
A revised Version can now be found at
Contact: Krishnaprasad Thirunarayan (Prasad),
Email: tkprasad@cs.wright.edu, phone: (513)-873-5109
URL: ftp://ftp.cs.wright.edu/pub/vhdl/
Files: VHDL93_SWI_2.7.14.tar.gz and README_SWI_2.7.14
Contact: Krishnaprasad Thirunarayan (Prasad),
Email: tkprasad@cs.wright.edu, phone: (513)-873-5109
URL: http://www.cs.wright.edu/people/faculty/tkprasad
The tools are available from
Contact: Email: sprudel@c-lab.de
URL: http://home.wtal.de/software-solutions/vhdl-parser
Contact: Email: grimm@ti.informatik.uni-frankfurt.de
URL: http://www.ti.informatik.uni-frankfurt.de/grimm/hybrid.html
Contact: Email: phil.wilsey@uc.edu
URL: http://www.ececs.uc.edu/~paw/suave
URL: http://poppy.snu.ac.kr/vdt-ivsim/vhdlsim.html
URL: ftp://poppy.snu.ac.kr/pub/vhdl/
URL: http://www.gnu.org/software/electric/electric.html
URL: http://www.staticfreesoft.com/
A Macintosh build of the Electric VLSI design tools is available from
URL: http://members.aol.com/djohn4077/html/electric.html
URL: http://www.ececs.uc.edu/~paw/savant
URL: ftp://ftp.ececs.uc.edu/pub/users/dmartin/
URL: http://www.cliftonlabs.com/savant/download/
The package VHDL-mode adds support for VHDL editing to GNU Emacs or XEmacs. It includes the following features:
URL: http://www.vim.org/
URL: http://nedit.org
GRASP is available for Unix (SPARC SunOS, SPARC Solaris, SGI Irix, X86 Linux, IBM AIX, DEC Alpha (Digital UNIX and Linux), Power MachTen 4.1) and for Win95/NT.
The Prism Editor is an 'environmentally friendly' shareware editor designed for Windows NT/95/98. It has a lot of features like code formatting, color syntax highlighting, column editing, block commenting/uncommenting. Currently it supports VHDL, Verilog and ABEL and any custom language. Further, VHDL HLP (see Section 1.5) may be used to add context sensitive help to the editor.
URL: http://www.e93.org/
URL: http://c3iwww.epfl.ch/people/martin/gumm.html
A version v1.1.1 (based on MVP v1.1) updated for USA A size paper and
assoaciated font bugs is available at
URL: http://vhdl.org/vi/vhdlsynth/mvp_v1_1_1.tar.gz
URL: ftp://vhdl.org/pub/vhdlsynth/mvp_v1_1_1.tar.gz
Another version v1.3.3 (based on previous versions from P.S. Elliot
and M. Gumm) by N.J.H.M. van Beurden can be downloaded from
URL: http://www.djnickmanns.cjb.net/
URL: http://djnickmanns.webjump.com/
Contact: Nick van Beurden, djnickmanns@email.com
URL: http://www.djnickmanns.cjb.net/
URL: http://djnickmanns.webjump.com/
Contact: Michael Knieser, Email: knieser@alpha.ces.cwru.edu
There are differnt version for VHDL 1076/87 and VHDL 1076/93 available
URL: http://www-inf.enst.fr/~demaille/a2ps/
URL: http://schwick.home.cern.ch/schwick/vhdldoc/Welcome.html
User reported that html files created by VHDLDOC are not compatible with Windows because of the generated file names. To fix this problem, the following awk script may be applied on the output files (posted by Ben Cohen to comp.lang.vhdl):
FNR == 1 {
file = FILENAME ; gsub( /::/, "__", file)
}
{
gsub( /::/, "__" )
gsub("%3A%3A", "__")
print > file
}
usage: awk -f fixhtml.awk html_files
Contact: Professor J. R. Armstrong, Bradley Department of
Electrical Engineering, Virginia Tech, Blacksburg, VA. 24061-0111,
phone: (540) 231-4723, fax: (540) 231-3362, Email: jra@vt.edu
URL: ftp://digres3.visc.vt.edu/pub/suite/vpi.tar
See also FAQ Part 1, Section 4.4.
URL: ftp://ftp.ececs.uc.edu:/pub/users/paw/software/vests.tgz.
URL: http://tech-www.informatik.uni-hamburg.de/vhdl/vhdl.html.
Contact: Jon Connell:jco@egnetz.uebemc.siemens.de
URL: http://bear.ces.cwru.edu/tools.html
URL: ftp://alpha.ces.cwru.edu/pub/VHDL/contrib/vhdl2html.tar.gz
Contribution are welcommed in /incoming (management by
herve@erm1.u-strasbg.fr) Suggestions and encouragments at
herve@erm1.u-strasbg.fr.
The database structure and contents are:
Contact: Email: herve@erm1.u-strasbg.fr
URL: ftp://erm1.u-strasbg.fr/pub/vhdl/
URL: http://erm1.u-strasbg.fr/db/
Contact: Cristian Ghezzi, Email: http://www.ghezzi.net/contact/index.htm
URL: http://www.ghezzi.net/pro/v2c/index.htm
Contact: Email: idass@xs4all.nl
URL: http://www.xs4all.nl/~averschu/idass/
FMF provides:
Contact: Email: rick.munden@vhdl.org
URL: http://vhdl.org/fmf
Contact: Email: chein@atl.lmco.com
URL: http://www.atl.external.lmco.com/rassp/vgui/index.html
Contact: Email: dmurray@iol.ie
URL: http://www.iol.ie/~dmurray/Prism/VHDL_Help.html
URL: http://rk.gsfc.nasa.gov/richcontent/Software_Content/KPP.htm
Further, the "EEdesign" at http://www.eedesign.com/ and the "Programmable Logic Jump Station" at http://www.optimagic.com are good web sources for informations on EDA tools.
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Accolade Design Automation, Inc.
550 Kirkland Way, Suite 200
Kirkland, WA 98033
USA
(425) 828-2122, (800) 470-2686
(425) 739-2163 FAX
http://www.acc-eda.com
Email: info@acc-eda.com
WWW: http://www.acc-eda.com
Japan Distributor:
InterLink, Inc.
1-5-21-1325 Mori Isogo-Ku
Yokohama 235 JAPAN
Phone: 81-45-40-28220
Accolade Design Automation, Inc. develops and markets high-performance
tools for VHDL and FPGA users. Products include a Microsoft Windows
(3.1, `95 and NT compatible) VHDL simulator in Personal and Professional
editions. The PeakVHDL simulator uses direct-compile technology, and
includes a source code browser, integrated 'make' facilities, and
integrated source file editor. The PeakFPGA synthesis product integrates
directly with PeakVHDL to provide a combined simulation and synthesis
environment for popular FPGA devices including Xilinx, Altera, Actel,
Lattice, Lucent and AMD. The Accolade Design Automation Web Site
http://www.acc-eda.com includes a free Introduction to VHDL
tutorial. Evaluation software is available, as is a textbook titled
"VHDL Made Easy!". Call or email for special low-cost educational
programs and packages.
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Aldec, Inc.
Corporate Headquarters
2230 Corporate Circle
Henderson, NV 89014
USA
Tel: (702) 990-4400
Toll Free: (800) 487-8743
Fax: (702) 990-4414
email: sales@aldec.com
web: www.aldec.com
Aldec, Inc., an 18-year EDA tool provider, is committed to delivering
high-performance, HDL-based design verification software for UNIX,
Linux and Windows platforms. Aldec is dedicated and responsive to
serving its customers' needs. It is recognized that to be productive
in today's market and to best serve customers in the future, new
technologies and innovations that go beyond traditional methods of
conducting business in the EDA industry must be pursued. Aldec is
committed to customer service and is actively developing a company
that will evolve along with its customers' designs.
********************************************************************
Alternative System Concepts, Inc.
PO Box 128 Windham NH 03087
tel (603) 437-2234 fax (603) 437-2722
Email: info@ascinc.com
WWW: http://www.ascinc.com
verilog2vhdl : verilog2vhdl translates hierarchical Verilog HDL to
VHDL by using an HDL object kernel which converts the input to an
intermediate format and then back to the other HDL. It makes a full
translation of structural Verilog, and a partial translation of
behavioral Verilog. It supports all synthesizable Verilog as a subset
and uses a combination of IEEE and tool-specific VHDL packages to
perform the translation. VHDL that is created by verilog2vhdl is
functionally equivalent to input Verilog, and because of one-to-one
mapping of Verilog to VHDL, output VHDL is easy to
understand. Comments are preserved and placed after the line in the
translated code most closely matching the design intent. Test benches
can be translated also to verify that the output is correct. Output
VHDL is IEEE 1076-1993 compliant. Node-locked and floating licenses
are available for HP-UX, Solaris, SunOS and Windows NT platforms.
VHDL2verilog: VHDL2verilog translates hierarchical VHDL (full
structural, part RTL) to Verilog HDL. Verilog that is created by
VHDL2verilog is functionally equivalent to input VHDL. Comments are
preserved and placed after the line in the translated code most
closely matching the design intent. Test benches can be translated
also to verify that the output is correct. Both IEEE Std 1076-1993 or
IEEE Std 1076-1987 compliant VHDLs are processed by the system and
output Verilog is compatible with any Verilog-XL compatible
simulator. Node-locked and floating licenses are available for HP-UX,
Solaris, SunOS and Windows NT platforms.
VBIT®: JTAG Test Synthesis for ASIC and IC Designers. VBIT®, which was
the industry's first RT level JTAG Test Synthesis tool, is available
directly from the developer ASC. The product features automatic
boundary scan test logic insertion synthesis by a tool using
technology independent IEEE 1149.1 macros to read VHDL or Verilog
input and produce corresponding RT Level VHDL or Verilog output. A
Simulation Testbench is created in Verilog or VHDL to test the
Boundary Scan Circuitry. A BSDL output file is also created for easy
interface to Board Level ATE and creating test vectors. VBIT® also
supports custom mapping to vendor-specific JTAG cell libraries and
custom interfaces for internal scan, memory and logic BIST. VBIT®
frees engineers from learning the tedious details of IEEE 1149.1
standard and manually inserting boundary scan test logic into their
ASIC, IC or MCM designs in an error-free rapid way. VBIT® scan
implementation at the RT level promotes design re-use. Tools that
insert boundary scan test at the gate level are used too late in the
design cycle to be truly technology independent. Furthermore, by
implementing boundary scan before logic synthesis, the designers can
synthesize functional core logic and test logic concurrently and avoid
timing and area violations in the entire chip. This saves costly
design iterations. Node-locked and floating licenses are available for
HP-UX, Solaris, and SunOS platforms.
FRITS: FRITS is an object-oriented framework to interface with other
EDA tools and facilitate rapid development. FRITS translates Verilog
HDL or VHDL descriptions into an intermediate format (common object
format) and stores the data in an object kernel in memory. The object
kernel is accessible to the EDA tool developer via an Application
Program Interface (API). FRITS also provides an elegant mechanism for
easy extraction of the stored design data. All operations by FRITS are
fast.
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Associated Professional Systems (APS)
3003 Latrobe Court
Abingdon, Maryland 21009
USA
Phone: 410-515-3883
Fax: 410-661-2760
Email: eda@associatedpro.com
APS develops FPGA test boards and packages them with EDA software
at very low prices. The APS-X84 XILINX Foundation Kits offer VHDL
Schematic capture, simulator, ABEL HDL, XACT router, and VHDL multimedia
tutorial plus the X84 ISA FPGA test utility board for prices as low as
$650.00. The kit comes with VHDL examples and C code to control and
download to the FPGA board from either the supplied XCHECKER cable or
from the PC ISA bus.
Check out the details at http://www.associatedpro.com/.
These deals can't be beat!
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Cadence Design Systems, Inc.
HDL Design Group
270 Billerica Road
Chelmsford MA 01824
508-667-8811
OR
555 River Oaks Pkwy.
San Jose, Calif. 951134
Eileen Elam (Public relations representative)
(408) 943-1234
Germany:
Mr. Grothe
phone: 02236 68051 seems now: 02236/962130 (Vertrieb)
Leapfrog - Full IEEE 1076 Simulation Environment Using Native Compiled Code
Synergy - VHDL and Verilog Logic Synthesis and Optimization
Verilog-XL - Verilog HDL and accelerated gate simulator
NCSim - native-compiled Verilog and VHDL simulation in the same kernel:
completely unified mixed-language simulation kernel supporting
VHDL 93, etc.
Envisia Ambit - VHDL & Verilog, high-capacity synthesis
Envisia PKS - Ambit synthesis with knowledge of the physical (layout)
dimension
Affirma FormalCheck - Model checking of VHDL and Verilog designs
Affirma Heck - Equivalence checking of VHDL & Verilog designs
Affirma HAL - HDL Analysis and Lint tool for both VHDL and Verilog
Valid (part of CADENCE now)
2820 Orchard Pkwy.
San Jose, Calif. 95134
Germany:
Muenchen,
phone: 089/710050 seems now: 089/570960 (Applikation)
compiler, simulator
Now sells Intermetrics tools
www: http://www.cadence.com/
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Cypress Semiconductor
Contact: Cypress Semiconductor Corporation
3901 N. First St.
San Jose, California 95134, U.S.A
Phone: (408) 943-2600
Fax : (408) 943-2741
- Information is also available from any of our sales offices Worldwide -
Warp2: Warp2 is a state-of-the-art VHDL compiler for designing with
Cypress PROMs and PLDs. Warp2 utilizes a proper subset
of IEEE 1076 VHDL as its Hardware Description Language (HDL) for its design
entry. Warp2 accepts VHDL input, synthesizes and optimizes the entered
design, and outputs an industry standard JEDEC map for the desired device.
This JEDEC file may then be simulated with the Cypress NOVA simulator
(included in Warp2).
Warp2 is available on PC(Windows) and Sun platforms.
www: http://www.cypress.com/
********************************************************************
Dolphin Integration
BP 65, ZIRST
39, avenue du Granier,
38242 MEYLAN, FRANCE.
Tel : +33 (0)4 76 41 10 96
Fax: +33 (0)4 76 90 29 65
WWW: http://www.dolphin.fr
Email: solution@dolphin.fr
Product:
SMASH (TM) is a mixed-signal multi-level simulator for ASICs, systems
and PCBs. SMASH can simulate circuits with parts described in SPICE
format, parts in Verilog-HDL, parts in VHDL, and parts in VHDL-AMS.
SMASH also supports true analog behavioral modeling in ABCD (based on
C language). Complex systems, built using 'silicon IP' delivered in
various formats, can be described most efficiently using the right
level of modeling and abstraction for each part. SMASH is a single-
process tool, and does not suffer from the complexity issues associated
with backplane solutions.
It delivers unprecedented performance for mixed-signal simulation based
on standard formats.
SMASH is available on Windows 9x/NT/2000, and also on Sun Solaris
machines. It is interfaced with popular schematic entry packages, such
as Cohesion Chip Designer. Evaluation versions (functional but limited
to small circuits) are available from the Web site
(http://www.dolphin.fr/medal/smash/smash_overview.html)
and also numerous application notes. Call or email for special
conditions applicable to educational use.
********************************************************************
Doulos Ltd
Church Hatch
22 Market Place
Ringwood
Hampshire
BH24 1AW
Tel : +44 (0)1425 471223
Fax : +44 (0)1425 471573
Email : info@doulos.com
WWW : http://www.doulos.com
Having built a formidable reputation for high quality, application
based VHDL, Verilog® and SystemC training, Doulos continues to develop
courses and project services for engineers pushing the boundaries of
new technology and methodologies. Doulos is independent of tool and
technology vendors, so all course attendees can learn using the tools
of their choice. Public courses are run across Europe, in the UK,
France, Germany and The Netherlands, and customised onsite courses can
be delivered worldwide.
Courses available (duration in days in brackets):
Foundation Level: (Preparatory training for design environment)
-----------------------
Essential Digital Design Techniques (2)
Essential Perl (3)
Essential Tcl/Tk (coming soon)
PaceMaker multi-media CBT (Verilog or VHDL, self teach)
Standard Level: (Beginner to full project readiness)
---------------------
Introduction to VHDL: A Foundation for PLD or ASIC design (2)
Further VHDL: Essential training for a PLD or ASIC design project (3)
Comprehensive VHDL: The above two modules together (5)
Comprehensive Verilog : Beginner to full PLD/ASIC project readiness (4)
Introduction to C/C++ for Hardware Engineers: enough C/C++ to
understand SystemC, or other C-based design tools (2)
SystemC : Use of SystemC for design and modelling (3)
Comprehensive SystemC : The above two modules together (5)
VHDL-AMS Workshop: Introduction to VHDL-AMS (2)
Expert Level: (Advanced design and verification techniques)
-----------------
Expert VHDL Design: Writing for Advanced Synthesis and Re-use (2)
Expert VHDL Verification: Advanced testbenches/modelling using VHDL (3)
Expert VHDL: The above two modules together (5)
Expert Verilog Design: Writing for Advanced Synthesis and Re-use (2)
Expert Verilog Verification: Advanced testbenches/modelling using VHDL
(3)
Expert Verilog: The above two modules together (5)
Xilinx TechClass: Using VHDL with Xilinx Architectures (2 or 3)
Altera TechClass: Using VHDL with Altera Architectures (2)
Course Materials
----------------
Comprehensive, fully indexed course notes (ideal as a reference manual).
Workbook packed with exercises (50% of the course is hands-on).
Doulos Golden Reference Guide (language, syntax, semantics, tips).
Tool Tour guides (to support your choice of tools and technologies).
Multi-media CD-ROM (an optional course preparation and refresher aid).
Publications
--------------
VHDL Pacemaker: multimedia VHDL tutorial on CD-ROM
HDL Pacemaker: multimedia Verilog tutorial on CD-ROM
VHDL and Verilog Golden Reference Guides
Partner companies
-----------------
Doulos has associate companies in France, Germany and The Netherlands
(SystemC courses only). Courses may be delivered in English, French,
or German.
France
---------
Francois Durif
AmbLot SARL
166 Boulevard du Montparnasse
F-75014
Paris, France
Tel : +33 (0)1 42795748
Fax : +33 (0)142795747
http://www.amblot.com
Germany
------------
Gerhard Wagner
Mikroelektronik Akademie
Garbsener Landstrasse 10
Hannover 30419
Germany
Tel : +49 (0) 511 277 1970
Fax: +49 (0) 511 277 1699
http://www.meak.de
The Netherlands (SystemC courses only)
----------------------
Clemens Stemerdink
Signa Technology
Lansinkesweg 4
PO Box 960
7550 AZ Hengelo (0)
The Netherlands
Tel: + 31 74 2555 699
Fax: + 31 74 2555 698
http://www.signa-tech.nl
DS Diagonal Systems AG
Tumigerstr. 71
CH-8606 Greifensee
Switzerland
Phone +41 1 905 60 60
Fax +41 1 905 60 69
WWW: http://www.diagonal.com/
E-mail (from all countries): info@diagonal.ch
Products:
BestBench is a VHDL testbench design- and analysis-tool that allows
to design and debug a testbench independently from the circuit design in
an earlier stage of the design process.
Unlike the manual and tedious testbench design, BestBench automates
the process by creating self-checking, reactive and stand-alone VHDL
testbenches.
BestBench is available for Solaris, SunOS, HP-UX and Windows NT.
WAVE-Link provides a bidirectional link from your simulation environment
to the HP16500 Logic Analyzer. It enables the design engineers to
download simulation data on the HP16500. Furthermore, WAVE-Link allows
to compare the response data measured by the HP16500 with the expected
simulation data.
WAVE-Link is available for SunOS and HP-UX.
BestLink/81200 allows to reuse VCD simulation data directly in the
HP81200 data generator/analyzer platform.
BestLink/81200 is available for Solaris, SunOS and HP-UX..
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EASICS, the VHDL Design Company.
Easics is an independent ASIC design company and offers a variety of
services related to the design of digital ASICs. These services
include the design of ASICs (up to a testable netlist) and FPGAs
(including prototyping), VHDL-based design consulting and ASIC design
feasibility studies.
Easics has a track record of ASIC designs in telecommunications (ATM,
SONET, SDH), bus interfaces and Digital Signal Processing applications.
For more information, look at our WWW-site http://www.easics.com/
or contact Lode Lauwers, General Manager (mailto:lode@easics.be),
Interleuvenlaan 86, B-3001 Leuven, BELGIUM
Tel +32-16-395 633, Fax +32-16-395 619
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Esperan
Unit 1
Hilldrop Lane
Ramsbury
Wiltshire
SN8 2RB
United Kingdom
Tel: +44 (0)1672 520101
Fax: +44 (0)1672 521039
Email: info@esperan.com
WWW: http://www.esperan.com
Esperan provides the highest quality and broadest range of leading
edge, vendor independent methodology training to the electronic design
community. We recognise the need for education covering the widest
possible range of electronic design methodologies.
Education is Esperan's sole mission allowing us to develop a style of
business which gives you the best possible return on your investment
with us.
Key Issues that set us apart:
High value, expert trainers
Well structured courses and reference materials
Personal and flexible approach
One stop shop
Courses available across Europe and North America
Complete service
Vendor independent approach
Visit out web site (http://www.esperan.com) to obtain full
details of the courses we offer:
VHDL Language Courses
Verilog Language Courses
Hardware Design Courses
ASIC Design Courses
FPGA/CPLD Technology and Design
Design Environment Courses:- PERL and Tcl/TK
********************************************************************
Exemplar Logic
Exemplar Logic pioneered the approach of applying logic synthesis techniques
to FPGA design. Today, it continues to develop and market logic synthesis
software, as well as, other design automation tools for the high-level
design (HLD) solution for FPGA, CPLD, and ASIC devices. Exemplar Logic's
software products offer customer improved time-to-market, reduce development
costs, and enhanced product quality. Supported platforms include UNIX (HP,
Sun) platforms in server and non-server environments, Windows NT, Windows
95, and Windows 98. Employees hail from semiconductor and EDA companies,
with specific expertise in software tools research and development,
manufacturing, marketing, and sales.
Visit the Exemplar Logic website (http://www.exemplar.com) for more
information or contact:
Exemplar Logic, Inc.
880 Ridder Park Drive
San Jose, CA 95131
1-800-632-3742
+44 1276 28899
info@exemplar.com
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Frontier Design
Frontier Design offers design, analysis and implementation tools, reusable
cores and design services to developers of leading edge telecommunication,
consumer and multimedia products. The company has developed state-of-the-art
algorithm compiler technology and has acquired unique application expertise
to meet the demanding design requirements in today's products.
The A|RT product line is an exciting family of products from Frontier
Design. A|RT stands for Algorithm-to-RT (register transfer) and embodies
Frontier's unique Algorithm-to-Silicon design methodology. The A|RT products
allow driving the HDL-based hardware design process directly from a C-code
specification of the algorithm. This significantly reduces the design-time
that is required to move algorithms into ASIC and FPGA implementations!
The family consists of :
ART Library : Fixed-point data type extension to ANSI C++. Bit-accurate
modeling of any width and precision including analysis and statistics.
ART Builder : Automatic ANSI-C++ and SystemC-to-HDL. Produces hierarchical
Mealy Machine for ASIC and FPGA.
ART Designer : Proven ANSI-C++ and SystemC-based architectural exploration.
Interactive C to HDL design flow for ASIC and FPGA.
Visit Frontier Design's Website at http://www.frontierd.com or contact
info@frontierd.com for more information.
Contacts:
USA:
Frontier Design Inc
100 Rialto Place, Suite 815
Melbourne FL 32901 - USA
Tel: +1.407.728.7750
Fax: +1.407.728.9670
Europe:
Frontier Design BVBA
Abdijstraat 34
3001 Heverlee
Belgium
Tel: +32.16.39.14.11
Fax: +32.16.40.60.76
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FTL Systems, Inc.
Contact: 924 Sierra Lane NE
Rochester, MN 55906
products@ftlsys.com
Main Number: +1 507 288 3154
Web: http://www.ftlsystems.com
Distributors available in North America and Japan (see WWW for details)
Products:
VHDL Complete OEM Analyzer/Elaborator (Fall 1996 Release)
VHDL Optimizing Compiler/Simulator (Early 1997 Release)
Other VHDL and Verilog products coming soon...
Public Service: VHDL-93, VHDL-AMS Validation Suite (1997 Release)
Glad to meet you at:
EuroDAC
US DAC
ASP DAC
VIUF/IVC
********************************************************************
Full Circuit Ltd
Chippenham
UK
Phone: +44 1249 720161
Fax: +44 7020 966228
Email: sales@fullcircuit.com
WWW: http://www.fullcircuit.com
VHDL Test Bench Tool
A tool to generate test benches that is both low-cost and unlike other
tools not constraining. Price 1/1/2001 is GBP80, $120 approx.
The tool generates fully functional VHDL but VHDL simple enough for
hand editing to be used to expand its functionality without limit.
The actual complex test vectors are stored in a separate file. Plus,
to make use of this flexibility, the test vectors can include
variables (e.g. integers, times, etc.) in addition to the UUT input
and output signals.
Complex signal relationships can easily be defined and again are not
constrained to a fixed set of constructs. This includes loops and
loops within loops. The loop counter can be used in the definition of
the signals. The test bench can be modular and individual modules
checked separately. A graphical plot of the test bench can be
displayed which is especially useful when looping is used.
A limited demo version is available and 30 day trial unlimited
licenses available by using the form.
Screenshots, worked example, downloads and license requests:
http://www.fullcircuit.com/TBtool.htm
The Test Bench tool program requires Excel 97+ so PC or MAC. No
knowledge of Excel is required.
In addition Full Circuit can provide bespoke VHDL IP, digital design,
analog design, and software. The web site also has some useful
freeware for PC (not VHDL related).
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Green Mountain Computing Systems, Inc.
83 River Road Apt. C
Essex Junction, VT 05452
Email: support@gmvhdl.com
WWW: http://www.gmvhdl.com/
Products
Green Mountain VHDL Compiler, Professional Edition This
professional-level IEEE VHDL simulator based on direct compile
technology provides fast simulation and advanced debugging features.
Currently available for Linux only (Windows version to be released).
Green Mountain VHDL Compiler, Educational Edition This edition
provides a lost-cost solution to VHDL beginners while providing full
support for the most commonly used features of VHDL. Currently
available for DOS and Linux.
********************************************************************
I-LOGIX
3 Riverside Drive
Andover, MA 01810
Tel. 978-682-2100
Fax. 978-682-5995
Statemate MAGNUM, a graphical behavioral modeling tool allows
hardware engineers to design with the precise graphical language of
STATECHARTS- a powerful extension of state transition diagrams.
Designers can create behavioral and functional models of
circuits, analyze the design using the simulation and dynamic
analysis capabilities proving that the design is correct before
code generation. Statemate MAGNUM then automatically generates
VHDL and VERILOG from the models both of which are fully compatible
with industry leading HDL simulation and synthesis tools.
www: http://www.ilogix.com/
********************************************************************
Integrated Circuit Design Consulting
http://www.kfu.com/~pharvey/resume.html
ASIC and VLSI design and verification using Verilog, VHDL, Synopsys,
Cadence, SPICE, etc.
********************************************************************
interHDL, Inc.
4984 El Camino Real
Suite 210
Los Altos, CA 94022-1433 USA
Tel: 415 428 4200
Fax: 415 428 4201
Email: info@interhdl.com
Ftp site: http://ftp.interhdl.com
Web page: http://www.interhdl.com
V to VH: Verilog to VHDL translator. Converts Verilog designs into
equivalent VHDL designs. Covers about 95% of the language including
the full structural and synthesizable subsets. The output VHDL code is
semantically and synthesis-wise equivalent to Verilog source, and is
very readable.
V to VL: VHDL to Verilog translator. Converts VHDL designs into
equivalent Verilog designs. Covers about 95% of the language including
the full structural and synthesizable subsets. The output Verilog code
is semantically and synthesis-wise equivalent to VHDL source, and is
very readable. Translation include generate statements, enumerations,
aggregate constants, etc. Comments are being preserved in the output
code.
********************************************************************
JRS Research Laboratories Inc.
2300 East Katella Ave., Suite 300
Anaheim, CA 92806-6048
Telephone (714) 704-1670
FAX (714) 704-1675
email: debbie@jrs.com
www: http://www.jrs.com/
********************************************************************
********************************************************************
Paul J. Menchini
Menchini & Associates Email: mench@mench.com
P.O. Box 71767 Voice: +1 919-479-1670
Durham, NC 27722-1767 Pager: +1 800-306-8494
USA Fax: +1 919-479-1671
WWW: http://www.mench.com
Mr. Menchini is an independent EDA Consultant with over seventeen years
of industrial EDA experience, specializing in the hardware description
languages VHDL and Verilog, and in high-level design methodologies.
He offers training, custom code and model development, and marketing
and technology consulting to EDA companies and users. His current and
former clients include Chrysalis Symbolic Design, DEC, Ikos, Research
Triangle Institute, Rosemount Aerospace, Synopsys, Tellabs, Thinking
Machines, TSSI, VHDL International, Viewlogic, and Zycad.
Mr. Menchini, who holds Bachelor's and Master's degrees from Stanford
University, is a member of IEEE (Senior Member), CS, ACM, IFIP Working
Group 10.2, and the Association for Automated Reasoning.
********************************************************************
MCC Microelectronics and Computer Technology Corp.
3500 West Balcones Center Dr.
Austin, Texas 78759
USA
Phone: +1 (512) 338 3598
e-mail: ask@mcc.com
simulator
www: http://www.mcc.com/
********************************************************************
Model Technology Incorporated
8905 S.W. Nimbus Ave, Suite 150
Beaverton, OR. 97008-7100 USA
Model Technology is the market leader in VHDL according to Dataquest
based on units and revenue. V-System is considered the most popular
VHDL simulator with over 11,000 revenue units sold worldwide and is
available on Workstation (HP, SUN Solaris, SUNOS5, and RS600) and PC
(x86 and Pentium based Windows 3.1, 95, and NT).
Model Technology sells a full line of HDL solutions for VHDL, Verilog,
and Mixed HDL simulation.
V-System is sold direct through Value-Added Resellers and through
OEM relationships such as Mentor Graphics, Exemplar, Data-I/O and
Escalade.
For more product information as well as who to contact: please
visit our home page at http://www.model.com,
email us at sales@model.com, or call us at 1-503-641-1340
********************************************************************
Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070-7777
for System-1076 and QuickVHDL
contact: Brian Caslis (brian_caslis@mentorg.com)
phone: hone: (503)685-1404 Fax: (503)685-1268
WWW: http://www.mentor.com/
for VHDLsim
contact: John Harris (john_harris@mentog.com)
phone: 503-685-4735
Germany:
Duesseldorf Sales Office
phone: 0211/591011
Fully integrated compiler/simulator/debugger design development system:
System-1076 - QuickSim-II based VHDL. Source-level debugger, supporting
VHDL concurrent events. Integrated in the Concurrent
Design(TM) environment - available now.
VHDLsim - Explorer Lsim based VHDL. Focused on IC design, VHDLsim is
integrated within the GDT design environment, and
supports the use of VHDL models with analog and M models in
the same design.
AutoLogic VHDL - VHDL synthesis
VHDLNet - netlist schematics into VHDL structural description
Design Architect - VHDL oriented text editor (and schematic editor)
QuickVHDL - Full IEEE 1076 Simulation Environment using Direct-Compiled
Code Technology. Includes integration with Design Architect
for entry and AutoLogic VHDL for synthesis. Available September
1993
********************************************************************
Papillon Research Corp. - Specialists in Hardware Engineering
142-Q North Rd.
Sudbury, MA 01776
ph: 978-371-9115
fax: 978-371-9175
Email: info@papillonresearch.com
WWW: http://www.papillonresearch.com
SERVICES:
Full product design including: architecture, ASIC, FPGA, mechanical,
and analog design, EMI design toward agency compliance, device
modeling, synthesizable modeling - all hardware related services.
PRODUCTS:
VHDL models: R3051 family, 29030, 79C940, CY7C960 & 964, VME bus,
others. The RXI/RXD chipset for the IDTR3051 family of RISC
processors provides DRAM/VRAM controller, I/O control, etc.
********************************************************************
Pittsburgh University of [PD/SW?]
Prof. Steven Levitan,
Dept. of Electrical Engineering
348 Benedum Engineering Hall
Univ. of Pitsburgh, 15261
Email: vhdl@ee.pitt.edu
see anonymous ftp: ee.pitt.edu (130.49.15.1) in pub/vhdl-info for files
README, letter.txt, license.PS, assurance.PS ...
not public domain, but 150$
analyzer/simulator and sources
********************************************************************
Productivity Engineering
Gesellschaft fuer Prozessintegration mbH
Benzstrasse 31
D-71083 Herrenberg
Telefon: ++49 / 7032 / 27 98 - 13
Telefax: ++49 / 7032 / 27 98 - 29
Email: Michael.Koch@PE-GmbH.com
WWW: http://www.PE-GmbH.com
Productivity Engineering is offering training, consulting-services and
software for quality and productivity enhancements within the process
of developing electronic components. Productivity Engineering has got
access to 15 experienced specialists in the area electronic design
automation, engineering data management and product data management.
Productivity Engineering is a neutral and independent service-company,
providing professional consulting and high-tech products.
Electronic Design Automation
----------------------------
Services provided within the EDA-Market are Turn-Key-Designs,
Project-Coaching, Hardware-Design, Library-Development for synthesis &
simulation as well as dataconversion tools and services for
pcb-databases to convert between leading eda-tool-suppliers. Running
VHDL- and Verilog-Design-Seminars on a regular basis in cooperation
with Doulos provides an actual overview of available
design-technologies as well as flexibility in using different
design-environments.
Methodology training
--------------------
Through a long cooperation with DOULOS (since 1993) we supply full
range of DOULOS-VHDL and Verilog methodology training in central
Europe, which could be adapted to the application areas of our
customers. These trainings classes are tool independent; different
design tools within one course are offered on a regular basis to
enhance experience. With the four and five-days-classes a multimedia
CD-ROM for preparantion and as a reference is supplied. Technology
guides offer a short introduction to backend FPGA-tools as well as an
introduction to FPGA architectures and coding for these FPGA
architectures. The workshops focus on the stuff presented so far and
show the application with practical examples developed by experienced
designers.
Application Support
-------------------
Within the application support we help our customers through
HDL-Coding-Standards, HDL-Code-Reviews and Design-Flow-Optimization.
HDL-Coding-Standards are of importance when emphasizing design reuse
through HDL-code reuse or when porting HDL-code to different
technologies or different simulators or synthesis tools.
We offer feasability studies and cost-analysis for FPGA- and
ASIC-Design-projects.
Product development
-------------------
Starting from specification we implement our customers product with a
turn-key-approach with fixed pricing. We even work out the
specification verbally or as a behavioural model of the design in
colaboration with our customer. Our consultants join your project
teams and strengthen your knowledge and enhancing the design capacity
of your company. We offer flexible add-on-resources for RTL-coding as
well as Testbench-Development.
During our projects you will get into touch with our technical
management, thus enhancing the effectivness of our work through short
responses to your requirements.
We employ specialists, with great experience caused by consultancy
project within the large american and german semiconductors. We have
application know how in Multimedia, PCI-bus-systems and PCMCIA.
Productivity Engineering succeeded in automotive application projects
as well as space- and air-industry and telecommunications.
********************************************************************
Qualis Design Corpration
PO Box 4444
Beaverton, OR, USA, 97075-4444
(503) 531-0377 fax: (503) 629-5525
Email: info@qualis.com
WWW: http://www.qualis.com
Overview
Qualis Design Corp of Beaverton, OR, offers high quality expert
consulting services in all aspects of using HDLs (both VHDL and
Verilog) including training, design environment, code management,
tooling, tool integration, behavioral modeling, test planning,
testbench infrastructure, testcase implementation, synthesis,
gate-level verification and more...
Training
Our classes differ from the traditional bottom-up, gate-to-behavioral
HDL training approach and reverses the flow starting with high-level
descriptions, testbench and top-down methodology. We feel this
high-level approach to training better fits an advanced design process
encouraging students to learn a methodology, and not just a
language. More than 70% of the time is spent on hands-on exercises
using the latest version of state-of-the-art VHDL, Verilog and
synthesis systems.
High-Level Design Using VHDL (5 days)
High-Level Design Using Verilog (5 days)
Advanced Techniques Using VHDL (3 days)
Advanced Techniques Using Verilog (3 days)
Products
VHDL language Quick Reference Card pub/qrcs
1164-based packages Quick Reference Card pub/qrcs
Verilog language Quick Reference Card pub/qrcs
Makefile generator for VHDL models pub/vhdl/vmk
********************************************************************
Sandstrom Engineering
3611 Vista Drive
Manhattan Beach, CA 90266-3245
voice 310.545.7108
email johan@sandstrom.org
fax 310.546.7396
website http://www.sandstrom.org
PreSynth.vhd supplements simulation by analyzing your RTL code.
It checks for nonsense constructs, the dreaded "reset problem",
non-synthesizable constructs, and performs hundreds of
lint-type checks. It also permits you to use an expanded subset
of VHDL, which PreSynth.vhd converts to synthesizable VHDL.
Consulting available.
********************************************************************
Saros Technology Ltd.
Business and Technology Centre
Stevenage
Herts
SG1 2DX
United Kingdom
Phone : ++44 (0)1438 746433
FAX: ++44 (0)1438 310093
Email : 100135.1052@compuserve.com
Contact : Chris Rose
Products :
Saros Technology Ltd. Specialise in the provision of a complete range
of VHDL development tools for the PC and Workstation platforms. As
the sole UK distributor for Model Technology, Exemlar Logic and
Translogic products we offer design entry, simulation and synthesis
tools for FPGA and ASIC design.
Saros Technology have also developed and offer a VHDL context
sensitive editor for the PC under Windows. VHDL Turbo Writer comprises
the powerful Codewright Editor from Premia corp, providing a fully
featured, multi window, multi document text editor with line numbers
and colour coding. This is enhanced by a rich set of VHDL templates,
integration with the Model Technology VHDL compiler and full error
detection within the editor environment.
Price L495 with volume discounts for 5 or more.
********************************************************************
SEE Technologies see Summit Design.
********************************************************************
Seeds VHDL ENvironment (SVEN)
Seed Solutions, Inc.
7505 Sherman Road
Chesterland, OH 44026
216-729-7500
Commercial parser
********************************************************************
Semantic Designs, Inc.
12636 Research Blvd #C214
Austin, Texas 78759
USA
Phone: 512-250-1018
Fax: 512-250-1191
Email: info@semdesigns.com
Semantic Designs provides software tools for
automating the analysis/modification/synthesis
of large scale specifications in many languages,
including VHDL and Verilog.
In particular, the DMS Reengineering Toolkit
(http://www.semdesigns.com/Products/DMS/DMSToolkit.html)
can parse arbitrary languages, automatically build compiler-like
Abstract Syntax Trees (ASTs), carry out analyses and surface-syntax
transforms on ASTs, and prettyprint the ASTs back to source language
form, for specifications of up to 2 million lines.
This tool is ideal for constructing custom analyzers and/or synthesizers.
Since DMS handle multiple languages (including C/C++, Java, Ada, ...),
and can have custom languages easily added as well,
it would be ideally suited as the foundation for CoDesign
applications.
www: http://www.semdesigns.com
********************************************************************
Seodu Logic, Inc.
http://www.seodu.co.kr
MyCAD PC based Toolset and Environment for VHDL Simulation, Synthesis etc.
********************************************************************
SICAN GmbH
Garbsener Landstr. 10
39419 Hannover
Phone: +49-511/277-1491
Fax: +49-511/277-2490
Email: info@sican.de
WWW: http://www.sican.de
USA:
SICAN Microelectronics Corp.
400 Oyster Point Blvd., Suite 512
So San Francisco, CA 94080
Phone: +81-650 871-1494
Fax: +81-650 871-1504
WWW: http://www.sican-micro.com
Email: info@sican-micro.com
Company Overview SICAN is a microelectronic design and technology
licensing company, specializing in communications, digital signal
processing, multimedia and networking applications. We provide our
targeted markets with leading edge design solutions by combining
state-of-the-art Design Methodology with highly optimized Core
Technology.
VHDL Products Digital Design Services In the recent five years
we have completed over 200 Digital VHDL-Designs including
synthesis. You can participate in our VHDL Design Experience by
realizing Turnkey Projects with us or by hiring our experienced
engineers as a Consultant or as a Designer in one of your inhouse
projects. In addition, you can order Training Services (VHDL,
VerilogHDL, Synthesis etc.) presented by our highly experienced
Senior Engineers.
DesignObjectsTM SICAN's DesignObjectsTM give design teams
a new alternative. Now, it is possible to buy synthesizable,
technology independant cores (VHDL and/or VerilogHDL) to quickly
integrate standards-based functionality required in a design.
DesignObjectsTM from SICAN encompass a broad spectrum of
technologies:
* Audio Decoders (e. g.MPEG-2 Layer 1&2 + Dolby AC-3 5.1 Channels)
* Broadband Access Functions (e. g. QAM-Demodulator)
* Bus Interfaces (e. g. PCI, USB, IEEE1394, CAN Bus Controler,
IIC Master / Slave Interface)
* Cryptographic Functions (e. g. DVB Descrambler)
* Digital Photography (e. g. JPEG Video Decoder with Color Space)
* General Purpose Microcontroller (e. g. 8051 Microcontroller)
* Industrial Functions (e. g. Motor Control Module, Pulse Width Modulation)
* Multimedia Accelerators (e. g. Video Conferencing Hybrid Accelerator)
* RAM Interfaces (e. g. SDRAM Timing Generator)
* Telecommunication/Communication/ATM (e. g. UTOPIA Interface)
* Video Decoders (e. g. MPEG-2 Video Decoder with Letterbox Features)
* Video Encoders (e. g. MPEG-1 Video Encoder)
* Video Processors (e. g. PAL/NTSC Video Encoder Interface)
DesignObjectsTM can be delivered as an all-inclusive assembly of
netlist or RTL source code, technical specifications, test benches,
synthesis scripts and application support.
Any further questions? Don't hesitate to contact us at:
Phone +49-511/277-1491
or visit our web-page http://www.sican.de
********************************************************************
Silicon System Solutions P/L
2/12 Wattle Valley Road
Canterbury Victoria 3126, Australia
Phone: +61 3 9888 4774
Fax: +61 3 9888 4224
Email: info@silicon-systems.com
WWW: http://www.silicon-systems.com
Products and services
* VHDL Cores (IP)
Fast-track to your system integration, with a selection of Synthesis
and Simulation Cores tuned to fit your needs.
* FPGA and ASIC design consultants
Our design experts are ready to help you with CPLD/FPGA and ASIC
development. Specify the models you require, and use our design
experts as a dedicated resource in your project development.
* ED4W-HDL - Powerful HDL Editor for VHDL and Verilog
ED4W-HDL is a VHDL/Verilog Editor for WindowsNT/95 and Windows 3.1.
HDL extensions developed by ASIC/FPGA Designers at SSS, for
ASIC/FPGA Designers. A very effective productivity tool.
********************************************************************
SoftSmiths Pty. Ltd.
54 Wylma St.
Holland Pk. 4121
Australia
Phone: + 61 7 847 2990
Fax: + 61 7 847 2707
Email: info@softsmiths.oz.au
Products: VHDL Design Entry schematiX11-VHDL
An X11 Sun based VHDL design entry package for the
purpose of capturing VHDL designs in a graphical format and
writing VHDL netlist descriptions. Being in a graphical form
it is much simpler to transfer the design concepts to other
colleagues and maintain the design over the life time of the
product.
Allows direct access to and editing of the functional code for
any block at any level in the design hierarchy. Interfaces
with any third party VHDL simulator.
Cost effective site licences allow UNIX based productivity at
prices per user comparable to PC based products.
freely licenced copies of SoftSmiths' VHDLcapture tools are available for
anonymous ftp download from ftp.tmx.com.au /cust/softsmiths/
Educational Licence Restrictions apply, if you are in doubt
ask us first (info@softsmiths.oz.au). If you are a commercial site you may
download this software for evaluation purposes.
www: http://www.webventures.com.au/ElectTech/softsmiths/
********************************************************************
Summit Design, Inc.
9305 S.W. Gemini Drive
Beaverton, OR 97005-7158
USA
Telephone: 503-643-9281
FAX: 503-646-4954
Contact: (various)
Product Name: Visual HDL
Visual HDL[TM] integrates four graphical languages, a textual language,
a simulator and debugger, and code generators for VHDL and Verilog. It
uses a state-of-the-art, object-oriented user interface, featuring a
graphical design browser.
Visual HDL includes intelligent editors for input of block diagrams,
state diagrams, flowcharts, and truth tables, besides VHDL text. This
comprehensive set of languages helps you to work at any level of
abstraction, and to mix levels of abstraction.
With Visual HDL you can create a high level description of your
design and validate it by execution. An event-driven, interactive
simulator works in tandem with a source-level debugger for rapid
analysis of the system. While the simulator runs, you can set
breakpoints, modify existing signals and variables, single-step through
multiple execution threads, and trace various activities. Visual
feedback appears on your source descriptions, in the windows of their
editors, for easy tracing.
Following design verification, Visual HDL generates VHDL or Verilog
code customized for the commercial synthesis tool you specify.
Visual HDL is available for UNIX and for Microsoft Windows.
www: http://www.summit-design.com/
********************************************************************
SynaptiCAD Inc.
520 Prices Fork Rd #C4
Blacksburg, VA 24060
USA
Phone: (540)953-3390 or (800)804-7073
Fax: (540)953-3078,
Email: sales@syncad.com
WWW: http://www.syncad.com
VHDL Test Bench and Stimulus Generators
SynaptiCAD develops stimulus generators and test bench generators
for VHDL. SynaptiCAD's premier product TestBencher Pro, is a
self-testing multi-diagram test bench generator. TestBencher Pro can
detect glitches, bad logic levels, and violations of setup and hold
times in simulation output. Users draw inputs to a simulation and
specify expected simulation outputs using graphical constructs called
samples. TestBencher Pro generates VHDL test benches with extra code
which verifies that graphically-specified conditions are met by a
simulator's output. Users can concatenate timing diagrams together to
mimic a series of read/write bus cycles. TestBencher Pro also has
looping and conditional constructs that enable simulation results to
control what stimulus is applied next.
SynaptiCAD also offers WaveFormer Pro, a timing diagram editor and
VHDL stimulus generator. Users draw a timing diagram that represents the
input to a simulation. Then the user exports the timing data as a VHDL
process that contains either transport or wait statements. WaveFormer
Pro supports all VHDL data types. Even user defined types like "type
MyColor is (RED, BLUE, GREEN)" can be exported with both type and state
information. TestBencher Pro and WaveFormer Pro are offer three
different ways to enter signal waveforms: (1) a graphical environment
for drawing, (2) text based temporal equations, and (3) boolean
equations of other signals. Other simulator formats are also supported
including Verilog, SPICE, Viewlogic, Orcad, Mentor QuickSim, HP Logic
Analyzers, HP Pattern Generators, and more, so timing diagrams can be
reused at different times during design process.
For a FREE evaluation of WaveFormer Pro or TestBencher Pro, product info,
and pricing, check out our web site: http://www.syncad.com/
********************************************************************
Synopsys Inc.
USA
Synopsys, Inc.
700 East Middlefield Road
Mountain View, California 94043-4033 U.S.A.
Phone: (415)962-5000
FAX: (415)965-8637
Germany (moved)
Synopsys, GmbH
Stefan George Ring 2
D-8000 Muenchen 81 Germany
Phone: 89/9939120
FAX: 89/99391217
URL: http://www.synopsys.com/
Products:
Design Compiler - Constraint-Driven Logic Optimization (CMOS & GaAs)
VHDL Compiler - VHDL Logic Synthesis
HDL Compiler - Verilog HDL Synthesis
Test Compiler - Test Synthesis (Auto. Test insertion + ATPG)
VHDL System Simulator - 100% language compatible VHDL behavioral simulation
Cyclone - A cycle based VHDL simulator
********************************************************************
Translogic
Translogic BV Translogic USA Corp.
Keesomstraat 17 341 Tres Pinos Road
P.O. Box 620 Suite #202B, CA
6710 BP EDE 95023, Hollister
The Netherlands USA
Phone: +31 (0)318 642076 Phone: 831-636-4664
Fax: +31 (0)318 641761 Fax: 831-636-4625
e-mail: info@translogiccorp.com
web site: http://www.translogiccorp.com/
Products:
EASE/HDL: Easy to use graphical HDL entry tool. Generates VHDL and
Verilog output for both simulation and synthesis purposes. Featuring
hierarchy browsing and state machine diagrams. Reverse engineering,
automatically generating graphical blocks for inclusion in block
diagrams.
EALE/HDL: Language-sensitive text editor, featuring color
coding, undo/redo, multi-document edit, keyword templates, synthesis
templates, completely customizable user interface and an extensive
on-line help. Supports VDHL, Verilog, ABEL, C, as well as synthesis
script languages.
Products available on both PC and UNIX systems. For more information
or a free evaluation copy please visit our web site:
http://www.translogiccorp.com.
********************************************************************
Topdown Design Solutions, Inc.
71 Spit Brook Road, Suite 301
Nashua, NH 03060
Phone: (603) 888-8811
Fax: (603) 888-7694
contact: Frank Hrobak or Art Pisani
Products:
VHDL SelfStart_Kit - a self-paced tutorial to learn VHDL quickly and
easily,
VBAK/XILINX - An Xilinx XNF to VHDL translation, which allows VHDL
simulation of both pre- and post-layout designs, including full-timing
simulation models.
Universal DRAM VHDL source code model
QuickStart, QuickStart2+1 - VHDL education at your site!
Model Technology V-System VHDL Simulator - on PC/Windows and UNIX
platforms
Consulting + Custom Training services available, including VIP (VHDL
Insertion Program) as well as public training.
www: http://www.topdown.com/
********************************************************************
TransEDA, Inc.
Contact: Tom Borgstrom, John Molyneux
Address: 985 University Avenue, Los Gatos, CA 95032
Phone: 408-907-2000
Fax: 408-907-2085
Email: info@transeda.com
Web: http://www.transeda.com
Products:
Verification Navigator - Integrated Design Verification Environment
VN-Cover - Verilog and VHDL Code Coverage
VN-Check - Parametric Design Rule Checker for Verilog and VHDL
VN-Optimize - Test Suite Analysis & Optimization
VN-State - FSM Extraction and Coverage
VN-Activity - Circuit Activity Analysis
VN-Check - Stand alone Verilog and VHDL parametric design rule checker
State Navigator - Comprehensive FSM Debug and Verification Environment
********************************************************************
Valid see CADENCE (part of)
********************************************************************
Vanilla CAD Tools, Inc.
Rt. 4, Box 146
Saluda, SC 29138-9126 USA
803-445-7227
Email: vanilla@emeraldis.com
Vanilla VHDL is a complete implementation of the 1987 IEEE standard,
including configurations. Like the old MCC system, it is completely
text-based, with a gdb-like command set for its debugger/simulator.
Unlike MCC, it does not translate to C, but instead uses an interpreted
engine, since this simplifies debugger implementation and enhances
portability.
To fund further development of the tools, they are now commercially
available on the PC. A 386 or better is required. An introductory
price is in effect until July 30, 1995.
********************************************************************
Vantage Analysis Systems, Inc. (purchased by Viewlogic)
USA:
42808 Christy Street, Suite 200
Fremont, CA 94538
phone: +1(510) 659-0901 fax: (510) 659-0129
contact: John Willey
Europe:
UK:
Grove Court Business Centre
Hatfield Road
Slough
Berkshire SL1 1QU (UK)
France:
Daniel Langois
MISIL Design
2 Rue De La Couture Silic 301
94588 Rungis Cedex (France)
Sweden:
Lars Lindqvist :- Engineer
Hardi Electronics
P.O. Box 966
Varvadersvagen 4P
S-220 09 Lund (Sweden)
Phone +46 46 117790
Germany:
Klenzestrasse 11
8045 Ismaning b. Muenchen
089/99652217
Japan:
Okura & Co, Ltd
3-6 Ginza, 2 chome
Chuo-ku, Tokyo 104 (JAPAN)
phone: 011-81-3-566-6000, fax: 011-81-3-563-5447
Vantage Spreadsheet, 100% IEEE 1076 VHDL Source Code Debugger Concurrent
Compiler Network License
Integrated VHDL Schematics/Simulator Read/Write Mentor/Valid/EDIF Schematics
Logic Automation & ASIC libraries Hardware Modeler On Sun & HP machines
and Silicon Graphics, Apollo
********************************************************************
VAutomation Inc.
20 Trafalgar Square
Suite 443
Nashua, NH USA 03063
TEL:(603)882-2282 FAX:(603)882-1587
Email: info@VAutomation.com
Contact: Eric Ryherd
Supplier of Technology Independent Synthesizable VHDL Models
Models of complex functions such as 8-16 bit
Microprocessors and their peripherals.
www: http://www.vautomation.com
********************************************************************
VeriBest, Incorporated
USA:
6101 Lookout Road
Boulder, Colorado 80301
Phone: 303.581.2300
Fax: 303.581.9972
toll free: 800.VERIBEST
WWW: http://www.veribest.com
Email: info@veribest.com
United Kingdom:
44.1793.511199
Germany:
49.89.96284.0
France:
33.1.41.76.35.00
Nordic:
46.8.92.54.00
Asia/Pacific:
852.2.893.3621
Japan:
81.3.3797.5277
Company:
VeriBest, Inc. is a broad line supplier of EDA solutions that enable
companies to solve their critical business issues by doing more and
spending less. VeriBest pioneered the Windows NT EDA market by
introducing its VeriBest PCB design solution in 1994 and continues to
offer the best EDA price/performance available in the industry.
VHDL Products:
VeriBest Graphical High-Level Design: VeriBest Graphical High-Level
Design is a language independent, graphical, state-machine entry and
debug environment. VBGHLD includes a state table editor, a state diagram
editor and a state flow graph editor. VBGHLD is integrated with VeriBest
Design Capture to give you a single environment for your design
definition needs. VBGHLD outputs both VHDL and Verilog.
VeriBest VHDL:
Introduced at DAC '96, VeriBest VHDL is a VHDL 1076-93 compliant
simulator offering unique debug features such as a Network Traverser.
VBVHDL is an Windows NT-product and utilizes standard NT ease-of-use
features such as signal drag-n-drop into the various display and debug
features.
VeriBest High-Level Design:
VeriBest High-Level Design is a VHDL/Verilog synthesis application that
outputs VHDL and Verilog for post-synthesis simulation and outputs
data for the VeriBest Design Optimizer.
********************************************************************
VhdlCohen Training, Consulting, and Verification
* On Site Training for Synthesis, Testbench Designs, and design processes.
* On-site or e-commerce Consultant
Build Verification and Testbench Models in VHDL
RTL Design per Your Requirements
Code Reviews to Ensure Compliance to Requirements
(e.g., functional, readability, reusability, synthesizability,
completeness).
EDA Tool evaluation
------------------------------------------------------
VhdlCohen Training, Consulting, Verification
Ben Cohen vhdlcohen@aol.com (310) 721-4830
http://www.vhdlcohen.com/
Author of following textbooks:
VHDL Coding Styles and Methodologies, 2nd Edition,
isbn 0-7923-8474-1 Kluwer Academic Publishers, 1999
VHDL Answers to Frequently Asked Questions, 2nd Edition,
isbn 0-7923-8115-7 Kluwer Academic Publishers, 1998
********************************************************************
VHDL Technology Group
100 Brodhead Road, Suite 140
Bethlehem, PA 18017
Tel: 610-882-3130 Fax: 610-882-3133
Email: sales@vhdl.com
VitalGen(tm) v1.0, a high-end model generator , produces Vital 3.0
compliant models.
Sledgehammer: A language aware editor for VHDL, VERILOG, C and C++
developers. Runs under Microsoft Windows, Windows-NT and Windows-95.
Provides language specific keyword identification and template
expansion, keyword color coding, auto-indentation and multi-file
search & replace, to name a few of the many features. Priced
comparable to most PC office automation software.
Std_DevelopersKit: A collection of four packages:
(1) Std_IOpak: includes routines for text I/O
testbench development, and type conversions.
(2) Std_Mempak: routines which you can use to develop memory models.
SRAMs, DRAMS, ROMS, and VRAMs.
(3) Std_Regpak/Synth_Regpak: provides synthesizable datapath subprograms
(4) Std_Timing: provides routines to model device
timing and delays. Complements the VITAL packages.
Used by over 1000 engineers worldwide.
Supports: All major simulators.
www: http://www.vhdl.com/
********************************************************************
Viewlogic Systems Inc.
293 Boston Post Road West
Marlboro, MA 01752
phone: 508/480-0881 or 1-800-422-4660, FAX: 508/480-0882, TELEX 174242
Germany:
Viewlogic Systems GmbH
Muenchner Str. 12
85744 Muenchen-Unterfoehring
phone (49)-89-9572490 FAX (49)-89-95724949
Powerview - open framework based on CFI
ViewSim/VHDL: simulator (behavioural and structural)
ViewSynthesis, Silcsyn and ViewArchitect: FPGA, ASIC
and behavioural synthesis
Viewgen: schematic drawing synthesis (indirectly coupled to EDIF)
Export.1076: Automatic VHDL netlist generation from Viewlogic schematic
(which accepts EDIF)
ViewFSM: graphical behavioral modeling tool that allows you to draw
statecharts and automatically produce VHDL for simulation and
VHDL that is optimized for synthesis
********************************************************************
Vista Technologies, Inc.
USA:
1100 Woodfield Road, Suite 437
Schaumburg, IL 60173-5121
Phone: (708) 706-9300, fax: (708) 706-9317
contact: David Jakopac
Email: hdlinfo@vistatech.com
Japan:
Marubeni Hytech Corp.
Marubeni Hytech Bldg.
20-22, Koishikawa 4-Chome
Bunkyo-ku, Tokyo 112
JAPAN
Phone: 81-3-3817-4871, Fax: 81-3-3817-4880
Contact: Ken Sakamaki
Europe:
LEDA S.A.
Europarc, Bat. C
F-13013 Marseille
FRANCE
Phone: 33+ 91 06 26 73, Fax: 33+ 91 06 24 66
Contact: Olivier Thibault
All of Vista's tools generate VHDL suitable for simulation, with
optional generation specifically for synthesis. All of Vista's
tools allow users to import VHDL Packages so that custom types,
functions and procedures can be utilized.
StateVision: Graphical state machine editor. Generates VHDL from
bubble diagrams of concurrent state-machines for simulation or
synthesis. Open and customizable system. Can be integrated with
off-the-shelf VHDL simulators for a complete design and debug
environment (set breakpoints in states, step with animation,
etc.) Shipping 4Q94.
DesignVision: Graphical behavior modeling editor. Uses the
DesignVision methodology ("threads") for specifying behavior
graphically. Generates VHDL for simulation or synthesis. Open
and customizable system. Users can customize the generated VHDL
to their own style and build their own graphical primitives
(including how the primitives generate VHDL). Can be integrated
with off-the-shelf VHDL simulators for a complete design and
debug environment (set breakpoints in threads, step with
animation, etc.) Special introductory price through Oct. '94.
Shipping now.
Vista Model Creator: Spreadsheet-like interface that generates
VHDL from function and state machine tables for simulation or
synthesis. Compact representation ideal for ALUs, instruction
decoders, etc. Shipping now.
VHDL Language Assistant: Syntax-directed editor with built-in
knowledge of VHDL. Not just language templates, full VHDL-1076
built-in. No special representation: can read, edit and write
any VHDL file. Shipping now.
The VHDL Developer: Suite of tools that includes VHDL Language
Assistant and Source Code Library Manager. Shipping now.
The VHDL Developer Plus: Suite of tools that includes Vista Model
Creator, VHDL Language Assistant, and Source Code Library
Manager. Shipping now.
********************************************************************
Vital, Inc.
4109 Candlewyck Drive
Plano, TX 75024
U.S.A
Ph: +1 (214) 491-6907 Fax: +1 (214) 491-6909
Email: info@vital.com or owner-crisp-list@uunet.uu.net
CRiSP is a graphical file editor on various UNIX and Windows platforms,
which combines the power and flexibility of other editors such as
vi, or Emacs but in a user-friendly fashion.
CRiSPs' dynamic syntax coloring for VHDL adds a new dimension to
the coding cycle. You can print the VHDL code in color too !!.
The editor comes with advanced template editing for VHDL, and
has an extensible macro language to customize it to the users
environment.
********************************************************************
VIZEF Limited
The Old Coach House
Adwell
Thame
OXON
Tel: 44 (0)1844 281066
Fax: 44 (0)1844 281070
Email: steve@vizef.demon.co.uk
SpeedSim high speed cycle simulation for fast verification of RTL
Verilog. Typically 10-100 times faster than Verilog-XL.
Virtual-ICE, for co-verification of hardware and firmware. This tool
enables ASIC/Software designers to run their firmware with the RTL level
ASIC and a CPU/DSP core(s) of choice. Using this tool allows you to
start final firmware debug and software performance analysis before a
physical device (FPGA or engineering samples) is available.
FlowHDL graphical tool for RTL design and testbench capture using the
ASM methodology. VHDL and Verilog output targeted for user specified
synthesis environment. Design environment supports multiple interacting
state machines, data path specification, multiple clock domains,
sync/async reset specification, synthesis directives and much more.
********************************************************************
Walnut Creek CDROM
4041 Pike Lane, Suite E
Concord, CA 94520
800/786-9907 or 510/674-0783
FAX 510/674-0821
Email info@cdrom.com
ADA CDROM has (besides other stuff)
uc -- the University of Cincinnati VHDL repository
VHDL (VHSIC Hardware Description Language)
Vhdl Mailing list moved to vhdl-sw@ece.uc.edu. All messages to the
list will be automatically archived on ftp.ece.uc.edu.
These messages are located in /pub/mailing-lists/vhdl-sw directory.
ftp Archive moved to thor.ece.uc.edu
Eventually, the ftp archive will be moved to ftp.ece.uc.edu too.
NEW SUBSCRIPTIONS SHOULD BE SENT TO listserver@ece.uc.edu. THE BODY
OF THE MESSAGE SHOULD BE AS FOLLOWS: subscribe vhdl-sw Your-name
********************************************************************
X-Tek Engineering
X-HDL, Verilog to VHDL translator. X-HDL has the power to perform 100%
translation of your synthesizable Verilog code to VHDL. Also X-HDL
can translate non-synthesizable constructs such as delay statements
and display statements, with additional support coming in the near future.
X-HDL has an intuitive, X-Windows based user interface.
DEMO VERSIONS OF X-HDL FOR SUN AND HP PLATFORMS ARE NOW AVAILABLE
VIA http://www.x-tekcorp.com/download.htm
For additional information, send your request to:
thomasr@mail.msen.com
www: http://www.x-tekcorp.com/
********************************************************************
Zycad Corporation
(ZyCads VHDL SOFTware was sold to Synopsys)
47100 Bayside Parkway
Fremont, CA 94538-9942
USA
phone: 1(510)623-4400
fax: 1(510)623-4550
VIP VHDL Instruction Processor
hardware accelerators
********************************************************************
The following lists are (probably) incomplete. Therefore, if you have any additional information or find any errors or compiler missing: please send me a note. If you have good or bad experiences with this tools (particularly with free software) please let me know. Thanks for all corrections.
Further, the "ISD Magazine" at http://www.isdmag.com and the "Programmable Logic Jump Station" at http://www.optimagic.com are good web sources for information on EDA tools.
Here is a list of (more or less) free available compilers:
The commercial compilers are divided into three price categories:
| Price category | Range (USD) |
| A | $1 < $200 |
| B | $200 < $1000 |
| C | above $1000 |
See also Section 2. Companies and their products/services for additional information.
| Vendor | Product | Version | Type | Support | Remarks |
| MTI | ModelSim | 4.7x/5.1f/5.2x | Sim | 93 | |
| MTI | ModelSim | 5.1f | Sim | 93 | |
| Cadence | Leapfrog | ? | Sim | 93 | |
| Viewlogic | Speedwave | 6.206 | Sim | 87 | |
| Metamor | Metamor | ? | Syn | 93 | |
| Synopsys | DC | ? | Syn | 87 | '93 support announced |
| Synopsys | DC99 | Syn | 93 | ||
| Synopsys | FPGA Express | 2.1.x | Syn | 87+ | '93 support announced |
| Synopsys | FPGA Express | 3.4 | Syn | 87+ | improved '93 support |
| Synopsys | VSS | 1998.08 | Sim | 93 | |
| Exemplar | Galileo | 4.2 | Syn | 93 | |
| Exemplar | Leonardo | 4.2.x | Syn | 93 | |
| Exemplar | Spectrum | 1998.2 | Syn | 93 | |
| Synplicity | Synplify | ? | Syn | 93 |
"Type" is the type of the product:
See also Section 2. Companies and their products/services for additional information.