Nov 18, 2002
onlsbc1: CAMACコントローラのデバッグ用ツールの整備
--- デバッグ用ツール #1
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
(http://www-online.kek.jp/~inoue/para-CAMAC/
Work/CAMAC-debug.html)
高エネルギー加速器研究機構
素粒子原子核研究所
物理、オンライングループ
井上 栄二
目的
CAMACコントローラのデバッグツールを整備する。
(1). 構成
(2). 構築
(3). 実行
--------------------------------------------------------------------
(1). 構成
(1-1). 書き込みテスト用
キーボードから入力するパラメータ：
PCIアドレス： Hexの数値を入力
ライトデータ： Hexの数値を入力
(1-2). 読み出しテスト用
キーボードから入力するパラメータ：
PCIアドレス： Hexの数値を入力
(1-3). プラグアンドプレイの自動設定アドレスのチェック
[inoue@onlpara inoue]$ cat /proc/pci
PCI devices found:
Bus 0, device 0, function 0:
Host bridge: Intel Corp. 82845 845 (Brookdale) Chipset Host Bridge (rev 17).
Prefetchable 32 bit memory at 0xf8000000 [0xfbffffff].
Bus 0, device 1, function 0:
PCI bridge: Intel Corp. 82845 845 (Brookdale) Chipset AGP Bridge (rev 17).
Master Capable. Latency=64. Min Gnt=10.
Bus 0, device 29, function 0:
USB Controller: PCI device 8086:24c2 (Intel Corp.) (rev 1).
IRQ 11.
I/O at 0xe800 [0xe81f].
Bus 0, device 29, function 1:
USB Controller: PCI device 8086:24c4 (Intel Corp.) (rev 1).
IRQ 5.
I/O at 0xe880 [0xe89f].
Bus 0, device 29, function 2:
USB Controller: PCI device 8086:24c7 (Intel Corp.) (rev 1).
IRQ 9.
I/O at 0xec00 [0xec1f].
Bus 0, device 29, function 7:
USB Controller: PCI device 8086:24cd (Intel Corp.) (rev 1).
IRQ 10.
Non-prefetchable 32 bit memory at 0xfebffc00 [0xfebfffff].
Bus 0, device 30, function 0:
PCI bridge: Intel Corp. 82820 820 (Camino 2) Chipset PCI (rev 129).
Master Capable. No bursts. Min Gnt=6.
Bus 0, device 31, function 0:
ISA bridge: PCI device 8086:24c0 (Intel Corp.) (rev 1).
Bus 0, device 31, function 1:
IDE interface: PCI device 8086:24cb (Intel Corp.) (rev 1).
IRQ 9.
I/O at 0x0 [0x7].
I/O at 0x0 [0x3].
I/O at 0x0 [0x7].
I/O at 0x0 [0x3].
I/O at 0xffa0 [0xffaf].
Non-prefetchable 32 bit memory at 0x20000000 [0x200003ff].
Bus 0, device 31, function 3:
SMBus: PCI device 8086:24c3 (Intel Corp.) (rev 1).
IRQ 3.
I/O at 0xe000 [0xe01f].
Bus 0, device 31, function 5:
Multimedia audio controller: PCI device 8086:24c5 (Intel Corp.) (rev 1).
IRQ 3.
I/O at 0xe400 [0xe4ff].
I/O at 0xe080 [0xe0bf].
Non-prefetchable 32 bit memory at 0xfebff800 [0xfebff9ff].
Non-prefetchable 32 bit memory at 0xfebff400 [0xfebff4ff].
Bus 1, device 0, function 0:
VGA compatible controller: PCI device 10de:0253 (nVidia Corporation) (rev 16
3).
IRQ 11.
Master Capable. Latency=64. Min Gnt=5.Max Lat=1.
Non-prefetchable 32 bit memory at 0xfd000000 [0xfdffffff].
Prefetchable 32 bit memory at 0xe8000000 [0xefffffff].
Prefetchable 32 bit memory at 0xf4280000 [0xf42fffff].
Bus 2, device 2, function 0:
Ethernet controller: Intel Corp. 82557 [Ethernet Pro 100] (rev 8).
IRQ 9.
Master Capable. Latency=64. Min Gnt=8.Max Lat=56.
Non-prefetchable 32 bit memory at 0xfeaff000 [0xfeafffff].
I/O at 0xdc00 [0xdc3f].
Non-prefetchable 32 bit memory at 0xfe900000 [0xfe9fffff].
[inoue@onlpara inoue]$
(2). 構築
(2-1). I/Oポートアクセスのテスト
#include <stdio.h>
#include <sys/io.h>
/* #include <asm/io.h> */
main() {
unsigned char value8;
unsigned short value16;
unsigned int value32;
unsigned long valuelong;
/*
printf("size of char = %d, size of short = %d, size of int = %d, size of
long = %d\n", sizeof(char), sizeof(short), sizeof(int), sizeof(long));
*/
if( iopl(3) ){
printf("can not change the privilege level\n");
exit(0);
}
/* a = inb(0x70); */
/* a = (unsigned long) inb(0xe400); */
value8 = inb(0xe400);
value16 = inw(0xe400);
value32 = inl(0xe400);
printf("inb(0xe400) = %x, inw(0xe400) = %x, inl(0xe400) = %x\n", value
8, value16, value32);
/* outb(0x70,a); */
}
[inoue@onlpara CAMACDebug]$
[inoue@onlpara CAMACDebug]$ gcc -O -o t4 t4.c
[inoue@onlpara CAMACDebug]$
[root@onlpara CAMACDebug]# ./t4
inb(0xe400) = 90, inw(0xe400) = 90, inl(0xe400) = 90
[root@onlpara CAMACDebug]#
(2-2). I/Oポートアクセスのテスト(その２)
[inoue@onlpara CAMACDebug]$ pwd
/home/inoue/CAMACDebug
[inoue@onlpara CAMACDebug]$ cat t15.c
#include
#include
/* #include */
main(argc, argv)
int argc;
char *argv[];
{
unsigned int addr;
int rwf, qf;
unsigned int value32;
int loop;
loop = (argc > 1) ? atoi(argv[1]): 20;
if( iopl(3) ){
printf("can not change the privilege level\n");
exit(0);
}
while (loop-- > 0) {
rwf = 0;
rewind(stdin);
printf("Read(: enter '1') or Write(: enter '2') ?");
scanf("%d", &rwf);
switch ( rwf ){
case 1:
printf("Read: Address(hex)= ");
scanf("%x", &addr);
value32 = inl(addr);
printf("inl(0x%x) = %x\n", addr, value32);
break;
case 2:
printf("Write: Date(hex)= ");
scanf("%x", &value32);
printf("Write: Address(hex)= ");
scanf("%x", &addr);
/* outl(value32, addr); */
/* printf("Confirm: Address(hex)= %x, Data(hex)= %x\n", addr, va
lue32); */
printf("outl(0x%x, 0x%x)\n", addr, value32);
break;
default:
printf("Wrong Mode\n");
break;
}
printf("\n");
}
}
[inoue@onlpara CAMACDebug]$
[inoue@onlpara CAMACDebug]$ gcc -O -o t15 t15.c
[inoue@onlpara CAMACDebug]$
(3). 実行
[root@onlpara CAMACDebug]# ./t15
Read(: enter '1') or Write(: enter '2') ?1
Read: Address(hex)= e400
inl(0xe400) = 90
Read(: enter '1') or Write(: enter '2') ?1
Read: Address(hex)= febff800
inl(0xfebff800) = ffffffff
Read(: enter '1') or Write(: enter '2') ?2
Write: Date(hex)= abcd5678
Write: Address(hex)= 987def34
outl(0x987def34, 0xabcd5678)
Read(: enter '1') or Write(: enter '2') ?
[root@onlpara CAMACDebug]#
---xxxx